1. Field of the Invention
The present invention relates to a method of transferring data between a processor and a multi-level cache to increase the amount of time in which the processor is operating without stall.
2. Description of Related Art
Rapid generation and processing of three dimensional (3-D) images are becoming increasingly important to many computer applications. Games and entertainment software use 3-D images to add realism to the game. Businesses have also discovered that the use of three dimensional graphics can increase the effectiveness of business presentations and data analysis.
Generating three dimensional images requires that a processor generate a stream of data. This stream of data is transferred to a memory for later use by a graphics unit. The transferring of data must occur at high speeds forming an almost continuous flow to avoid jerky images.
Typically, the process of generating 3-D images includes receiving user input, determining new characteristics and requirements, and translating these requirements into different drawing primitives and drawing operations. In one method of generating 3-D images, a processor in a system generates a tessellated object list. The tessellated object list may list triangle meshes or discrete triangles. Alternatively, this list may include higher order surface representations such as polygons, and bezier patches.
In order to further define or manipulate a 3-D image, the processor or graphics processor in a graphics unit uses the triangle list to calculate a new list of triangles based on a desired rotation or translation. A graphics unit may further refine the list of triangles to add necessary attributes such as lighting, texture and transparency. The output of a graphics processor typically consists of grouping of screen pixel information such as pixel color.
High performance 3-D graphics applications require the flow of data from the system processor to the graphics processor to be properly pipelined. In order to avoid "jerky" movement, the pipelining of data must supply a graphics processor with an approximately continuous flow or steady stream of data. In high speed processors the point at which the data flow is slowest acts as a bottleneck. This bottleneck dictates the peak level of performance of the 3-D imaging system. Thus, it is desirable to pipeline graphic data in the most efficient way possible.
Traditional cache systems do not pipeline data through the cache system. In a traditional system, the cache may be in a write back mode or a write through mode. In a write back mode, only the cache is updated, the contents of main memory are not updated until specifically instructed. In a write through mode, the main memory is always updated. In a multiple cache system, such updating is dependent. Thus when the processor alters the contents of a first cache, simultaneous updates of the first cache to main memory and from the first cache to a second cache are accomplished. Such systems are slow because the contents of the first cache can only be emptied as fast as the main memory can accept new data preventing the processor from soon writing to the first cache.
As will be disclosed, the invention is a novel method of using multiple caches to facilitate the pipelining of data.